In a digital integrated circuit (IC), a microprocessor core of the circuit is connected to external pins of the IC through input/output (I/O) switching buffers which pass data from the core of the IC to external pins for transmission via external transmission lines to a receiving IC. The I/O switching buffers need a considerable amount of current in order to drive the high external loads. Power for the I/O switching buffers is provided by way of one or more pairs of supply lines comprising a drain (power) VDD and a source (ground) VSS which are in turn connected to respective external pins of the IC.
A number or array of such I/O switching buffers are commonly connected to the same VDD/VSS pair. However, the data input to some of the I/O switching buffers of the array can switch simultaneously from a logical HIGH state to a logical LOW state (i.e., a H-L transition). Many I/O switching buffers simultaneously performing the H-L transition can give rise to what is known as ground bounce (i.e., a temporary rise in the ground voltage) and thus increased noise. Conversely, the data input to the I/O switching buffers can switch simultaneously from the logical LOW state to the logical HIGH state (i.e., a L-H transition). Several I/O switching buffers simultaneously performing the L-H transition can give rise to what is known as a power droop and thus increased noise. In such circumstances, the ground bounce can also induce a false pulse in an output of an I/O switching buffer which is not switched with the others in the array and whose input switching state is in a “quiet low” condition. Similarly, a false pulse can also be induced in the output of an I/O switching buffer by a power droop when the input of the I/O switching buffer is in a “quiet high” condition. Such false pulses are passed via the transmission lines to the receiving IC which treats the false pulses as true pulses, resulting in a system error.
There are generally three types of I/O switching buffers which are commonly used in ICs. The first is termed an open drain buffer where the drain VDD is not critical and does not give rise to any power droop. In an open drain type of buffer the only concern is for the ground bounce. It will be appreciated that a simultaneously switched output (SSO) number for an open drain buffer refers to the number of I/O switched buffers which can be connected to a common source VSS.
The second type of buffer is termed an open source buffer. In an open source type of buffer the source VSS is not critical and does not give rise to a ground bounce signal. The open source type of buffer is only concerned with power droop. It will be appreciated that the SSO number for an open source buffer refers to the number of buffers which can be connected to a common drain VDD. In the third type of buffer, both the drain VDD and source VSS are of concern and consideration must be given to both power droop and ground bounce.
FIG. 1 shows a conventional array of I/O transistor switching buffers 10, 12, 14 and 16. Each I/O transistor switching buffer 10–16 has a respective input 20, 22, 24, and 26, and an output 30, 32, 34, and 36. Power is supplied via a drain VDD connected to one pin of the IC and a source (ground) VSS connected to a second pin of the IC.
Data signals are applied to the inputs of the buffers 10–16 and then to onward transmission lines (not shown) via the outputs 30–36 of the buffers 10–16. The voltage level at the input 20–26 of each buffer 10–16 would normally be either a “quiet high” (i.e., a logic one state) or a “quiet low” (i.e., a logic zero state).
A number of such buffer circuits 10–16 would be provided in an IC around the periphery to transmit data from the core of the IC to the external connection pins of the circuit for onward transmission to the remote receiving IC. The output 30–36 of each buffer circuit 10–16 is connected to its own external pin of the IC.
FIG. 2 pulse 2A shows a conventional data signal applied, for example, to the input 20 of the buffer circuit 10 to provide an output pulse on the buffer output 30 which would then be applied to the associated external pin of the IC containing the buffer 10. Pulses 2B, 2C and 2D show similar data signals applied to the inputs 22, 24 and 26 of the buffers 12, 14 and 16. If, as is shown in FIG. 2 pulses 2A to 2D, the H-L transitions (i.e., trailing edges) of the data signals coincide and thus the buffers 10 to 16 are switched simultaneously, then a ground bounce (i.e., a rise in the source voltage VSS immediately following the H-L transitions) can occur as shown in pulses 2E. Conversely, if the L-H transitions (i.e., leading edges) of the data signals coincide, then a power droop in the voltage VDD immediately following the L-H transitions can occur as shown in pulse 2F. If the L-H transitions occur a time T1, then the power droop occurs a short time afterwards at time TD. If the H-L transitions occur at a time T2, then the ground bounce occurs a short time afterwards at time TB.
A considerable amount of effort is invested in simultaneous switching output (SSO) analysis for each type of buffer in order to determine the maximum number of simultaneously switching buffers allowed to be connected via a common drain VDD or source VSS to the associated external power or ground pins. The number of switching buffers connected to a common drain VDD and/or source VSS is termed the SSO number and has to be determined during design of the IC. For example, in an eight-bit data bus it is quite possible to have seven I/O buffers switching simultaneously in the same direction (H-L or L-H) and all even buffers can therefore be considered as one SSO group. If the buffers are open drain and analysis has shown that a maximum of four I/O buffers can be connected to a single VSS pin then the SSO number is four and two ground pins will be required for this particular group. Conversely, if the buffers are open source and analysis has shown that a maximum of four I/O buffers can be connected to a single VDD pin then the SSO number is four and two source pins will be required for this particular group.
As will be appreciated, as the number of buffers which can switch simultaneously in the same direction increases, then the number of pairs of power and ground pins required will increase. In the example of FIG. 1, if analysis of the circuit has shown that the four buffers connected to the same VDD/VSS pair results in the ground bounce and/or power droop shown in pulses 2A–2F then more than one pair of power/ground pins would be required for this group. The analysis, in turn, results either in a limitation in the number of pins that can be used for transferring data from the IC or requires an increase in the size of the IC to accommodate the extra pins required.
One way of reducing the impact of simultaneous switching noise or system errors resulting from several buffers switching simultaneously is to stagger the input data transitions slightly in order to break up the SSO groups into smaller groups and reduce the rate of change of the supply current which occurs with simultaneous switching. Staggered input data transitions give rise to a delay in data transfer since delays have to be included in the IC in order to introduce the time variations in the switching pulses. Furthermore, compensating delay has to be introduced further along the transmission line in order to realign the pulses. It is also difficult to predict amount of delay required in order to avoid ground bounce or power droop, particularly when data is transferred at a variable speed. Compensating delay also requires the use of delay lines before the buffer circuits and after the buffer circuits which increases costs. It is also not possible to introduce such a staggered delay for the input switching pulses when processing synchronised signals.